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M66312P/FP
8-Bit LED Driver with Shift Register and Latched 3-State Outputs
REJ03F0178-0201 Rev.2.01 Mar 31, 2008
Description
M66312 is a LED array driver having a 8-bit serial input and parallel output shiftregister function with 3-state output latch. This product guarantees the output electric current of 16 mA which is sufficient for LED drive, capable of flowing 8 bits continuously at the same time, and use either of cathode common LED and anode common LED. In addition, as this product has been designed in complete CMOS, power consumption can be greatly reduced when compared with conventional BIPOLAR or Bi-CMOS products.
Features
* High output current IOL = 16 mA, IOH = -16 mA * High speed (clock frequency): 30 MHz (typ) (CL = 50 pF, VCC = 5 V) * Low power dissipation: 20 W/package (max) (VCC = 5 V, Ta = 25C, quiescent state) * 3-state output (except serial data output) * Wide operating temperature range: Ta = -40 to +85C
Application
LED array drive of PRINTER LED array drive of BUTTON TELEPHONE
REJ03F0178-0201 Rev.2.01 Mar 31, 2008 Page 1 of 8
M66312P/FP
Block Diagram
Parallel data outputs
QA QB QC QD QE QF QG QH
Serial data output
SQH VCC
15
1
2
3
4
5
6
7
9
16
0 CK D
0 CK D
0 CK D
0 CK D
0 CK D
0 CK D
0 CK D
0 CK D
1 CK DR
1 CK DR
1 CK DR
1 CK DR
1 CK DR
1 CK DR
1 CK DR
1 CK DR
13
OE
12
CKL
14
A
11
CKS
10
R
8
GND
Output Latch Serial enable clock data input input input
Shift clock input
Direct reset input
Pin Arrangement
M66312P/FP
QB 1 QC 2 QD 3 Parallel data outputs QE 4 QF 5 QG 6 QH 7 GND
8 QC QD QE QF QG QB Q A A OE CKL CKS
16
VCC Parallel data output Serial data input Output enable input Latch clock input Shift clock input Direct reset input
15 QA 14 A 13 OE 12 CKL 11 CKS 10 R 9
QH SQ R H
SQH Serial data output
(Top view) Outline: PRDP0016AA-A (16P4) PRSP0016DE-A (16P2N-A)
REJ03F0178-0201 Rev.2.01 Mar 31, 2008 Page 2 of 8
M66312P/FP
Functional Description
As M66312 uses silicon gate CMOS process, it realizes high-speed and high-output currents sufficient for LED drive while maintaining low power consumption and allowance for high noises. Each bit of a shiftregister consists of two flip-flops having independent clocks for shifting and latching. As for clock input, shift clock input CKS and latch clock input CKL are independent from each other, shift and latch operations being made when "L" changes to "H". Serial data input A is the data input of the first-step shiftregister and the signal of A shifts shiting registers one by one when a pulse is impressed to CKS. When A is "H", the signal of "H" shifts. When A is "L", the signal of "L" shifts. When the pulse is impressed to CKL, the contents of the shifting register at that time are stored in a latching register, and they appear in the output from QA through QH are 3-state outputs. To extend the number of bits, serial data output SQH is used to output the 8-bit of the shift register. By connecting CKS and CKL, the shift register state delayed by 1 clock cycle is output at QA through QH. When reset input R is low, shift register and SQH will be reset. To reset QA through QH to low-level, CKL must be changed from low-level to high-level after the shift register is reset by R. When output-enable input OE is high, QA through QH will become high impedance state, but SQH is not changed. Even if OE is changed, shift operation is not affected. Function Table (Note)
Input Operation Mode Reset Shift latch Shift t1 Latch t2 Shift t1 Latch t2 Latch t2 3 state R L X H H H H X CKS X X X X X CKL X X X X A X X H X L X X OE L L L L L L H QA QA0 L QA0 H QA0 L Z QB QB0 L QB0 qA0 QB0 qA Z
0
Parallel Data Output QC QC0 L QC0 qB0 QC0 qB Z
0
QD QD0 L QD0 qC0 QD0 qC Z
0
QE QE0 L QE0 qD0 QE0 qD Z
0
QF QF0 L QF0 qE0 QF0 qE Z
0
QG QG0 L QG0 qF0 QG0 qF
0
QH QH0 L QH0 qG0 QH0 qG Z
0
Serial Data Output SQH L L qG0 qG0 qG0 qG0 qH
operation Shift t1
Z
Note
: Change from low-level to high-level 0 Q : Output state Q before CKL changed X: Irrelevant 0 q : Contents of shift register before CKS changed q: Contents of shift register t1, t2: t2 is set after t1 is set Z: High impedance
REJ03F0178-0201 Rev.2.01 Mar 31, 2008 Page 3 of 8
M66312P/FP
Absolute Maximum Ratings
(Ta = -40 to +85C, unless otherwise noted)
Item Supply voltage Input voltage Output voltage Input protection diode current Output parasitic diode current Output current per output pin Supply/GND current Power dissipation Storage temperature range Note: QA to QH SQH Symbol VCC VI VO IIK IOK IO ICC Pd Tstg Ratings -0.5 to +7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -20 20 -20 20 35 25 132 500 -65 to +150 Unit V V V mA mA mA mA mW C VCC, GND
(Note)
Conditions
VI < 0 V VI > VCC VO < 0 V VO > VCC
M66312FP; Ta = -40 to +70C, Ta = 70 to 85C are derated at -6 mW/C.
Recommended Operating Conditions
(Ta = -40 to +85C, unless otherwise noted)
Item Supply voltage Input voltage Output voltage Operating temperature range Input rising and falling time VCC = 4.5 V VCC = 5.5 V Symbol VCC VI VO Topr tr, tf Min 4.5 0 0 -40 0 0 Limits Typ 5 -- -- -- -- -- Max 5.5 VCC VCC +85 500 400 Unit V V V C ns
REJ03F0178-0201 Rev.2.01 Mar 31, 2008 Page 4 of 8
M66312P/FP
Electrical Characteristics
(VCC = 4.5 to 5.5V, unless otherwise noted)
Limits Item High-level input voltage Low-level Input voltage High-level output voltage QA to QH High-level output voltage SQH Low-level output voltage QA to QH Low-level output voltage SQH High-level input current Low-level input current Off state highlevel output current QA to QH Off state lowlevel output current QA to QH Quiescent supply current VOH VOL VOL IIH IIL IOZH VCC-0.1 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.1 0.7
(note)
Sym bol VIH VIL VOH
Ta = 25C Min 0.70x VCC -- VCC-0.1 3.70(note) Typ -- -- -- -- Max -- 0.30xVCC -- --
Ta = -40 to +85C Min 0.70xVCC -- VCC-0.1 3.55(note) VCC-0.1 3.9 -- -- -- -- -- -- -- Max -- 0.30xVCC -- -- -- -- 0.1 0.85
(note)
Unit
Conditions VO = 0.1 V, VCC-0.1 V IO = 20 A VO = 0.1 V, VCC-0.1 V IO = 20 A VI = VIH, VIL VCC = 4.5 V IOH = -20 A IOH = -16 mA IOH = -20 A IOH = -4 mA IOL = 20 A IOL = 16 mA IOL = 20 A IOL = 4 mA
V V V
V V V A A A
VI = VIH, VIL VCC = 4.5 V VI = VIH, VIL VCC = 4.5 V VI = VIH, VIL VCC = 4.5 V
0.1 0.4 0.1 -0.1 1.0
0.1 0.5 1.0 -1.0 10.0
VI = VCC, VCC = 5.5 V VI = GND, VCC = 5.5 V VI = VIH, VIL VCC = 5.5 V VO = VCC
IOZL
--
--
-1.0
--
-10.0
A
VO = GND
ICC
--
--
4.0
--
40.0
A
VI = VCC, GND, VCC = 5.5 V
Note:
Limits of single PIN operating state
REJ03F0178-0201 Rev.2.01 Mar 31, 2008 Page 5 of 8
M66312P/FP
Switching Characteristics
(VCC = 5 V)
Limits Item Maximum clock frequency Low-level to high-level and high-level to low-level output propagation time CKS-SQH High-level to low-level output propagation time RSQH Low-level to high-level and high-level to low-level output propagation time CKL-QA to QH Output disable time from low-level and high-level OE-QA to QH Output enable time to lowlevel and high-level OE-QA to QH Note: Test Circuit
Input VCC Output VCC RL = 1 k SW1 PG 50 DUT SW2 GND CL RL = 1 k
Symbol fmax tPLH tPHL
Min 15 -- --
Ta = 25C Typ -- -- --
Max -- 70 70
Ta = -40 to +85C Min Max 12 -- -- -- 88 88
Unit MHz ns ns
Conditions CL = 50 pF CL = 15 pF
(Note)
tPHL
--
--
60
--
76
ns
tPLH tPHL
-- --
-- --
60 60
-- --
76 76
ns ns
CL = (Note)
50 pF
tPLZ tPHZ tPZL tPZH
-- -- -- --
-- -- -- --
50 50 56 56
-- -- -- --
64 64 70 70
ns ns ns ns
CL = 5 pF
(Note)
CL = 50 pF
(Note)
Item tPLH, tPHL tPLZ tPHZ tPZL tPZH
SW1 Open Close Open Close Open
SW2 Open Open Close Open Close
(1) The pulse generator (PG) has the following characteristics (10% to 90%): tr = 6 ns, tf = 6 ns (2) The capacitance CL includes stray wiring capacitance and the probe input capacitance.
Timing Requirements
(VCC = 5 V)
Limits Item CKS, CKL, R pulse width A setup time with respect to CKS CKS setup time with respect to CKL A hold time with respect to CKS R recovery time with respect to CKS Symbol tw tsu tsu th trec Min 32 40 40 10 20 Ta = 25C Typ -- -- -- -- -- Max -- -- -- -- -- Ta = -40 to +85C Min Max 40 50 50 10 26 -- -- -- -- -- Unit ns ns ns ns ns Conditions
REJ03F0178-0201 Rev.2.01 Mar 31, 2008 Page 6 of 8
M66312P/FP
Timing Chart
tw
VCC CKS
50% tPLH 50% 50% tPHL 50%
CKL
VCC
50%
GND VOH
GND
tPLH
SQH
VOH QA to QH
50% tPHL
50%
VOL
VOL VOH
tw
VCC R
50% 50% trec
QA to QH
50%
VOL
GND VCC VCC A GND
tsu th 50% 50%
CKS
tPHL
50%
GND VCC
50%
VOH SQH
50%
VOL
CKS
GND
VCC OE
50% tPZL 50%
GND
tPLZ
CKS QA to QH
tPZH 50% tPHZ 50% 90% 10%
VCC
50% tsu tw
GND VCC
VOL VOH CKL
QA to QH
50%
50%
GND
REJ03F0178-0201 Rev.2.01 Mar 31, 2008 Page 7 of 8
M66312P/FP
Package Dimensions
JEITA Package Code P-DIP16-6.3x19-2.54 RENESAS Code PRDP0016AA-A Previous Code 16P4 MASS[Typ.] 1.0g
16
9
1
8
*1
c
e1
E
*2 D
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
A2
A
Reference Symbol
Dimension in Millimeters
e SEATING PLANE
*3
b3
bp
*3
b2
e1 D E A A1 A2 bp b2 b3 c e L
L
A1
Min 7.32 18.8 6.15 0.51 0.4 0.9 1.4 0.22 0 2.29 3.0
Nom 7.62 19.0 6.3
Max 7.92 19.2 6.45 4.5
3.3 0.5 1.0 1.5 0.27 2.54
0.6 1.3 1.8 0.34 15 2.79
JEITA Package Code P-SOP16-5.3x10.1-1.27
RENESAS Code PRSP0016DE-A
Previous Code 16P2N-A
MASS[Typ.] 0.2g
16
9
HE
*1
E
F
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
1 Index mark
8 A2 A1
c
*2 D
Reference Symbol
Dimension in Millimeters
e
y
*3
bp
Detail F
D E A2 A1 A bp c HE e y L
Min Nom Max 10.0 10.1 10.2 5.2 5.3 5.4 1.8 0.1 0.2 0 2.1 0.35 0.4 0.5 0.18 0.2 0.25 0 8 7.5 7.8 8.1 1.12 1.27 1.42 0.1 0.4 0.6 0.8
A
REJ03F0178-0201 Rev.2.01 Mar 31, 2008 Page 8 of 8
L
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